The invention relates to a synchronous clock generator for digital signal multiplex devices comprising a first counter whose counting period corresponds to a block length of a pulse frame and which can be set into a prescribed counter reading, comprising a block counter controlled by said first counter and comprising a logic element connected to the outputs of the counters for generating working clock signals.
In digital signal multiplexers, a plurality of digital message streams are combined into a multiplex signal. As is known, digital information such as, for example, the frame identification word, the stuffing identifier bits as well as the stuffing and signalling bits must be inserted into the multiplex signal. Clock pulses produced in clock generators serve to mark these points in time. At the receive side, the multiplex signal must in turn be divided into a plurality of message streams and the auxiliary information must be evaluated at the correct time. The clock generators of a specific multiplexer stage required at the transmit and receive sides differ only slightly from one another. In contrast thereto, different multiplexers for different hierarchy stages exhibit different pulse frames which contain a different number of bits. The pulse frames in various hierarchy stages can differ both in the number of the transmitted blocks as well as in the number of the transmitted bits per block or in both. A separate clock generator has hitherto been developed for each multiplexer.